Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable Core.
J. C. Peña-RamosRamón Parra-MichelPublished in: ReConFig (2011)
Keyphrases
- digital signal processing
- network on chip
- power dissipation
- signal processing
- low power
- data flow
- image processing
- computer vision and image processing
- multi processor
- interconnection networks
- routing algorithm
- data transfer
- parallel computers
- cmos technology
- power consumption
- low cost
- network simulator
- computer vision
- single chip
- neural network
- real time
- computer systems
- pattern recognition
- graphical models
- high speed