A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption.
Kenta SogoAkihiro ToyaTakamaro KikkawaPublished in: ASP-DAC (2013)
Keyphrases
- power consumption
- power dissipation
- cmos technology
- power reduction
- low power
- nm technology
- end to end delay
- power management
- power saving
- energy efficiency
- battery life
- high speed
- battery powered
- delay insensitive
- energy saving
- circuit design
- data center
- packet loss
- analog vlsi
- low voltage
- single chip
- signal processing
- image processing
- clock gating
- real time