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High-speed CMOS track-and-hold with an offset cancellation replica circuit.
Mahzad Azarmehr
Rashid Rashidzadeh
Majid Ahmadi
Published in:
ISCAS (2010)
Keyphrases
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high speed
low power
frame rate
focal plane
real time
peer to peer
high speed networks
analog vlsi
neural network
evolutionary algorithm
load balancing
fault tolerance
database systems
response time
vlsi circuits