Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC.
Akram Ben AhmedBen Abdallah AbderazekKenichi KurodaPublished in: BWCCA (2010)
Keyphrases
- network on chip
- packet switched
- multi processor
- routing algorithm
- power dissipation
- network simulator
- low power
- shared memory
- design methodology
- real time
- efficient implementation
- design process
- hardware design
- cmos technology
- hardware and software
- hardware architecture
- ad hoc networks
- fault tolerant
- routing protocol