A FPGA based intra-parallel architecture for PageRank graph processing.

Guoqiang Mei Rui Hao Jiangwei Wang Hongwei Kan Rengang Li

Published in: EDGE (2020)

Keyphrases

parallel architecture
hardware implementation
random walk
parallel processing
web graph
link analysis

systolic array
shared memory
processing elements
directed graph
parallel implementation
high level synthesis

efficient implementation
synthetic aperture sonar
hardware architecture
distributed memory
field programmable gate array
pagerank algorithm

parallel algorithm
link structure
image processing algorithms
graph mining
neural network