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Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA.

Hao ZhangDongdong ChenSeok-Bum Ko
Published in: IET Comput. Digit. Tech. (2017)
Keyphrases
  • floating point
  • sparse matrices
  • square root
  • fixed point
  • power consumption
  • floating point unit
  • low cost
  • high speed
  • floating point arithmetic
  • computer vision
  • massively parallel
  • interval arithmetic