FPGA accelerator for floating-point matrix multiplication.
Zeljko JovanovicVeljko M. MilutinovicPublished in: IET Comput. Digit. Tech. (2012)
Keyphrases
- floating point
- matrix multiplication
- field programmable gate array
- hardware implementation
- message passing
- embedded systems
- square root
- parallel computing
- distributed memory
- image processing algorithms
- fixed point
- matrix factorization
- floating point unit
- parallel implementation
- computing systems
- graphics processing units
- sparse matrices
- massively parallel
- instruction set
- floating point arithmetic
- low cost
- distributed systems
- efficient implementation
- keypoints
- higher order