Cost-effective Resilient FPGA-based LDPC Decoder Architecture.
Eduardo Nunes de SouzaGabriel L. NazarPublished in: IOLTS (2019)
Keyphrases
- cost effective
- hardware architecture
- low cost
- low density parity check
- ldpc codes
- cost effectiveness
- hardware implementation
- fpga implementation
- hardware design
- distributed video coding
- real time
- hardware architectures
- vlsi architecture
- low complexity
- error correction
- turbo codes
- distributed source coding
- decoding algorithm
- wyner ziv
- video decoder
- error concealment
- environmentally friendly