Formalization and Model Checking of SysML State Machine Diagrams by CSP#.
Takahiro AndoHirokazu YatsuWeiqiang KongKenji HisazumiAkira FukudaPublished in: ICCSA (3) (2013)
Keyphrases
- state machine
- model checking
- finite state machines
- formal methods
- constraint satisfaction problems
- temporal logic
- model checker
- formal specification
- formal verification
- temporal properties
- finite state
- constraint satisfaction
- timed automata
- automated verification
- symbolic model checking
- constraint programming
- transition systems
- knowledge representation
- verification method
- reachability analysis
- computation tree logic
- modeling language
- fault tolerant
- reactive systems
- linear temporal logic
- np complete
- epistemic logic
- concurrent systems
- operational semantics
- bounded model checking
- np hard