A priority assignment strategy of processing elements over an on-chip bus.

Ya-Shu Chen Song-Jian Tang Shi-Wu Lo

Published in: SAC (2007)

Keyphrases

priority assignment
processing elements
high speed
massively parallel
functional units
linear array
parallel computers
low cost
parallel processors
content addressable memory
search space
search strategy
hardware architecture
higher priority
orders of magnitude
parallel architecture