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Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology.

Jaeduk HanNicholas SutardjaYue LuElad Alon
Published in: IEEE J. Solid State Circuits (2017)
Keyphrases
  • power consumption
  • cmos technology
  • data processing
  • high quality
  • low power
  • high speed
  • case study
  • low cost
  • multipath