A dynamic latched comparator for low supply voltages down to 0.45 V in 65-nm CMOS.

Yu Lin Kostas Doris Hans Hegt Arthur H. M. van Roermund

Published in: ISCAS (2012)

Keyphrases

case study
high speed
low cost
genetic algorithm
power consumption
real time
data mining
information systems
high resolution
dynamically changing
transmission line
circuit design
power supply
cmos technology