High-level aging estimation for FPGA-mapped designs.

Abdulazim Amouri Mehdi Baradaran Tahoori

Published in: FPL (2012)

Keyphrases

high level
low level
high speed
source code
higher level
robust estimation
data sets
low cost
real time
digital signal
estimation accuracy
wet lab
intermediate level
hardware design
field programmable gate array
estimation algorithm
estimation error
hardware implementation