Check and simulate: a case for incorporating model checking in network simulation.
Ahmed SobeihMahesh ViswanathanJennifer C. HouPublished in: MEMOCODE (2004)
Keyphrases
- model checking
- temporal logic
- finite state
- partial order reduction
- formal specification
- formal verification
- temporal properties
- model checker
- bounded model checking
- verification method
- computation tree logic
- transition systems
- pspace complete
- finite state machines
- epistemic logic
- timed automata
- asynchronous circuits
- symbolic model checking
- process algebra
- automated verification
- concurrent systems
- formal methods
- deterministic finite automaton
- communication networks
- reachability analysis
- reactive systems
- data flow