Adaptive Line Size Cache for Irregular References on Cell Multicore Processor.

Qian Cao Chongchong Zhao Junxiu Chen Yunxing Zhang Yi Chen

Published in: NPC (2010)

Keyphrases

memory management
hit rate
query processing
cell processor
memory hierarchy
high end
prefetching
cache misses
level parallelism
shared memory multiprocessors
computing power
data structure
shared memory
computer architecture
multithreading
memory access
memory requirements
computer systems