Combining PDR and reverse PDR for hardware model checking.
Tobias SeufertChristoph SchollPublished in: DATE (2018)
Keyphrases
- model checking
- temporal logic
- formal specification
- finite state
- formal verification
- model checker
- reachability analysis
- automated verification
- transition systems
- temporal properties
- partial order reduction
- computation tree logic
- symbolic model checking
- timed automata
- finite state machines
- verification method
- bounded model checking
- concurrent systems
- formal methods
- process algebra
- epistemic logic
- pspace complete
- asynchronous circuits
- linear temporal logic
- abstract interpretation
- deterministic finite automaton
- alternating time temporal logic
- software architecture