Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors.
Pegdwende Romaric NikiemaAngeliki KritikakouMarcello TraiolaOlivier SentieysPublished in: DSN-S (2023)
Keyphrases
- fine grained
- low complexity
- coarse grained
- vlsi architecture
- concurrency control
- access control
- computational complexity
- massively parallel
- motion estimation
- wireless video
- application specific
- parallel processing
- parallel algorithm
- distributed video coding
- markov random field
- parallel computing
- hardware architecture
- lower complexity
- low power consumption
- general purpose