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Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board.

Pawel ChodowiecKris GajPeter BellowsBrian Schott
Published in: ISC (2001)
Keyphrases
  • data sets
  • real world
  • network security
  • neural network
  • genetic algorithm
  • high speed
  • efficient implementation
  • hardware implementation