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Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product.

I. MamathaShikha TripathiT. S. B. SudarshanNikhil Bhattar
Published in: SIRS (2014)
Keyphrases
  • systolic array
  • parallel architecture
  • reconfigurable architecture
  • efficient implementation
  • data flow
  • neural network
  • image processing
  • feature extraction
  • pattern recognition
  • frequency domain
  • software agents