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Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors.

Miroslav N. VelevRandal E. Bryant
Published in: J. Symb. Comput. (2003)
Keyphrases
  • formal verification
  • boolean satisfiability
  • model checking
  • computer architecture
  • branch and bound algorithm
  • instruction set
  • level parallelism