Architectural Verification of Processors Using Symbolic Instruction Graphs.
Ashok K. ChandraVijay S. IyengarR. V. JawalekarMichael P. MullenIndira NairBarry K. RosenPublished in: ICCD (1994)
Keyphrases
- instruction set
- model checking
- graph theoretic
- parallel algorithm
- multimedia
- high level
- software architecture
- graph mining
- instructional design
- memory hierarchy
- formal methods
- face verification
- graph representation
- graph theory
- statistically significant
- neural network
- np hard
- single processor
- computer software
- signature verification
- random graphs
- high performance computing
- online learning
- shared memory
- graph matching
- cooperative learning
- symbolic representation
- parallel computing
- graph databases
- graph model