FPGA based implementation of decoder for array low-density parity-check codes.
Pankaj BhagawatMomin UppalGwan ChoiPublished in: ICASSP (5) (2005)
Keyphrases
- low density parity check
- ldpc codes
- decoding algorithm
- error correction
- channel coding
- vlsi architecture
- image transmission
- low complexity
- distributed video coding
- message passing
- channel capacity
- joint source channel coding
- error resilient
- turbo codes
- unequal error protection
- source coding
- error resilience
- error correcting
- physical layer
- low power
- bit error rate
- error propagation
- computational complexity