Approach for a Formal Verification of a Bit-serial Pipelined Architecture.
Henning ZabelAchim RettbergAlexander KruppPublished in: IESS (2007)
Keyphrases
- efficient implementation
- formal verification
- pipelined architecture
- hardware implementation
- model checking
- field programmable gate array
- automated verification
- model checker
- symbolic model checking
- bounded model checking
- temporal logic
- neural network
- program slicing
- pattern recognition
- signal processing
- real time
- case study
- bayesian networks
- machine learning