Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM.

Brian Johnson Brent Keeth Feng Lin Hua Zheng

Published in: ISSCC (2007)

Keyphrases

high speed
control system
preprocessing phase
multiscale
response time
data transfer
real time
optimal control
control theory
data sets
genetic algorithm
information systems
case study
multi agent
data acquisition
control problems