Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture.
Jakub ZádníkJarmo TakalaPublished in: ICASSP (2019)
Keyphrases
- low power
- single chip
- high speed
- vlsi architecture
- low cost
- signal processor
- power consumption
- cmos image sensor
- cmos technology
- gate array
- mixed signal
- nm technology
- logic circuits
- digital signal processing
- wireless transmission
- high power
- real time
- image sensor
- power management
- hardware and software
- delay insensitive
- vlsi circuits
- general purpose processors
- vlsi implementation
- signal processing
- instruction set
- low power consumption
- parallel processing
- general purpose
- image processing
- power dissipation