FPGA and ASIC implementation of robust invisible binary image watermarking algorithm using connectivity preserving criteria.
P. KarthigaikumarK. BaskaranPublished in: Microelectron. J. (2011)
Keyphrases
- hardware implementation
- hardware architecture
- xilinx virtex
- circuit design
- field programmable gate array
- single chip
- hardware design
- signal processing
- computationally efficient
- low power
- real time
- software implementation
- fpga implementation
- low cost
- image processing algorithms
- dedicated hardware
- hardware architectures
- pipelined architecture
- selection criteria
- robust estimation
- design methodology
- multi criteria
- efficient implementation
- connected components
- high speed
- design considerations
- image processing
- fpga technology
- neural network