Performance optimization of CNFET for ultra-low power reconfigurable architecture.

S. D. Pable Mohd. Hasan

Published in: ICCCS (2011)

Keyphrases

reconfigurable architecture
systolic array
ultra low power
optimization algorithm
optimization process
global optimization
optimization methods
constrained optimization
bayesian networks
probabilistic model
high speed
parallel algorithm
low power
discrete optimization
optimization strategies