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A 3.6-mW 6-GHz current-reuse VCO-buffer with improved load drivability in 65-nm CMOS.
Md. Tawfiq Amin
Pui-In Mak
Rui Paulo Martins
Published in:
Int. J. Circuit Theory Appl. (2015)
Keyphrases
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power consumption
low voltage
high speed
low power
power supply
power reduction
low cost
nm technology
clock frequency
load balancing
cmos technology
hd video
x ray
image sensor
circuit design
buffer size