Delay estimation and measurement circuit for a high-speed CMOS clocked comparator.
L. CronP. LaugierPietro Maris FerreiraFilipe Vinci dos SantosPhilippe BénabèsPublished in: ECCTD (2017)
Keyphrases
- high speed
- low power
- power dissipation
- data acquisition
- cmos technology
- power consumption
- vlsi circuits
- logic circuits
- frame rate
- focal plane
- single chip
- low cost
- delay insensitive
- measurement error
- accurate estimation
- real time
- mixed signal
- nm technology
- digital signal processing
- estimation accuracy
- estimation algorithm
- high speed networks
- robust estimation
- chip design
- image processing