Towards Verification of Bit-Slice Circuits-Time-Space Modal Model Checking Approach-.
Hiromi HiraishiPublished in: IEICE Trans. Inf. Syst. (1995)
Keyphrases
- model checking
- temporal logic
- transition systems
- automated verification
- asynchronous circuits
- formal verification
- verification method
- model checker
- modal logic
- formal specification
- temporal properties
- pspace complete
- finite state
- bounded model checking
- symbolic model checking
- concurrent systems
- process algebra
- finite state machines
- timed automata
- computation tree logic
- partial order reduction
- formal methods
- epistemic logic
- reachability analysis
- alternating time temporal logic
- reactive systems
- cl pc
- search space
- knowledge representation
- abstract interpretation
- coalition logic
- reinforcement learning