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Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning.

Mauro ChinosiRoberto ZafalonCarlo Guardiani
Published in: CICC (1999)
Keyphrases
  • spatio temporal
  • power consumption
  • single phase
  • hidden markov models
  • control method
  • power reduction
  • space time
  • model checking
  • power dissipation
  • chip design