A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches.
Hyunhee KimSungjun YounJihong KimPublished in: MEDEA@PACT (2008)
Keyphrases
- low power
- single chip
- embedded processors
- signal processor
- high speed
- low cost
- memory access
- power consumption
- shared memory
- multithreading
- mixed signal
- low power consumption
- cmos technology
- cmos image sensor
- memory subsystem
- caching scheme
- cache misses
- digital signal processing
- parallel computing
- parallel algorithm
- image sensor
- cache hit ratio
- logic circuits
- power reduction
- real time
- data access
- vlsi circuits
- ultra low power
- memory bandwidth
- prefetching
- vlsi architecture
- embedded systems
- nm technology
- power dissipation
- gate array