Block-Level Logic Extraction from CMOS VLSI Layouts.
Inderpreet BhasinJoseph G. TrontPublished in: VLSI Design (1994)
Keyphrases
- chip design
- vlsi circuits
- high speed
- delay insensitive
- single chip
- design methodology
- physical design
- random access memory
- logic programming
- low power
- information extraction
- vlsi design
- automatic extraction
- modal logic
- signal processing
- low cost
- classical logic
- focal plane
- asynchronous circuits
- power consumption
- circuit design
- multi valued
- automatically extracting
- real time