Hardware-friendly LDPC Decoding Scheduling for 5G HARQ Applications.
Cing-Yi LiangMao-Ruei LiHuang-Chang LeeHsin-Yu LeeYeong-Luh UengPublished in: ICASSP (2019)
Keyphrases
- ldpc codes
- low density parity check
- decoding algorithm
- scheduling problem
- hardware and software
- vlsi architecture
- low cost
- turbo codes
- error correction
- scheduling algorithm
- real time
- parallel processors
- image transmission
- channel coding
- vlsi implementation
- resource allocation
- heterogeneous computing
- parallel machines
- hardware implementation
- message passing
- low complexity
- video sequences
- distributed video coding
- computer systems