A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification.
Guang ZhuQuan PanJohn ZhuangCharlie ZhiC. Patrick YuePublished in: A-SSCC (2017)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- single chip
- high power
- low density parity check
- vlsi architecture
- logic circuits
- energy dissipation
- digital signal processing
- cmos technology
- low power consumption
- tree structured vector quantization
- rate allocation
- distributed video coding
- ldpc codes
- image sensor
- vlsi circuits
- distributed source coding
- gate array
- physical layer
- signal processing