Mapping for Maximum Performance on FPGA DSP Blocks.
Bajaj RonakSuhaib A. FahmyPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2016)
Keyphrases
- verilog hdl
- digital signal processing
- signal processing
- real time image processing
- systolic array
- high speed
- digital signal
- data flow
- image processing
- digital signal processors
- low cost
- field programmable gate array
- hardware implementation
- digital signal processor
- texas instruments
- low power consumption
- block size
- hardware design
- image blocks
- dct coefficients
- maximum number
- low power
- multiresolution
- multiscale