A low power W-band PLL with 17-mW in 65-nm CMOS technology.
Tao-Yao ChangChao-Shiun WangChorng-Kuang WangPublished in: A-SSCC (2011)
Keyphrases
- cmos technology
- low power
- power consumption
- low voltage
- single chip
- silicon on insulator
- power management
- power dissipation
- high speed
- low cost
- power reduction
- energy saving
- digital signal processing
- low power consumption
- mixed signal
- image sensor
- nm technology
- image processing
- hidden markov models
- power supply
- digital images