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A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs.
Himanshu Thapliyal
Vishal Verma
Hamid R. Arabnia
Published in:
CDES (2006)
Keyphrases
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floating point
fixed point
square root
field programmable gate array
instruction set
sparse matrices
floating point arithmetic
hardware implementation
interval arithmetic
signal processing