High-flexible hardware and instruction of composite Galois field multiplication targeted at symmetric crypto processor.
Yang SuBai-Long YangChen YangJing-Yuan HePublished in: J. Ambient Intell. Humaniz. Comput. (2021)
Keyphrases
- instruction set
- floating point
- galois field
- level parallelism
- memory hierarchy
- low cost
- single chip
- memory bandwidth
- integer arithmetic
- low power consumption
- hardware and software
- computer architecture
- computing power
- high end
- multi core processors
- embedded systems
- parallel processors
- real time
- processor core
- high speed
- cellular automata
- parallel architectures
- ibm zenterprise
- main memory
- memory subsystem
- lightweight
- digital signature
- ibm power processor
- central processor
- efficient implementation