Bounded depth circuits with weighted symmetric gates: Satisfiability, lower bounds and compression.
Takayuki SakaiKazuhisa SetoSuguru TamakiJunichi TeruyamaPublished in: J. Comput. Syst. Sci. (2019)
Keyphrases
- lower bound
- logic circuits
- upper bound
- image compression
- np hard
- branch and bound
- objective function
- data compression
- np complete
- satisfiability problem
- compression scheme
- depth map
- branch and bound algorithm
- high speed
- compression algorithm
- compression ratio
- depth information
- upper and lower bounds
- analog circuits
- image sequences
- online learning
- linear programming
- computational complexity
- delay insensitive