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Real-Time Visual Saliency Architecture for FPGA With Top-Down Attention Modulation.
Francisco Barranco
Javier Díaz
Begoña del Pino
Eduardo Ros
Published in:
IEEE Trans. Ind. Informatics (2014)
Keyphrases
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real time
visual saliency
dedicated hardware
pipelined architecture
fpga device
saliency map
fpga technology
xilinx virtex
hardware implementation
visual attention
field programmable gate array
eye movements
vision system
human visual system
natural scenes
natural images
multiscale
bayesian framework
high quality