Design of Low-Power Non-Binary LDPC Decoder Exploiting DRAM Refresh Rate Over-Scaling.
Wenjie HuangWeiguo TangJunlin ChenLei WangPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2019)
Keyphrases
- low power
- low density parity check
- non binary
- ldpc codes
- vlsi architecture
- single chip
- power consumption
- cmos technology
- decoding algorithm
- low cost
- low power consumption
- high speed
- logic circuits
- digital signal processing
- mixed signal
- power reduction
- power dissipation
- gate array
- constraint satisfaction problems
- real time
- ultra low power
- image sensor
- frequent pattern mining
- constraint programming
- data structure