A Scalable Symbolic Simulator for Verilog RTL.
Sasidhar SunkariSupratik ChakrabortyVivekananda M. VedulaKailasnath ManeparambilPublished in: MTV (2007)
Keyphrases
- hardware description language
- high level
- web scale
- highly scalable
- simulation environment
- symbolic representation
- connectionist systems
- hardware designs
- model based diagnosis
- integrated circuit
- low level
- artificial neural networks
- memory efficient
- intermediate level
- database systems
- social networks
- genetic algorithm