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FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing.

Welson SunMichael J. WirthlinStephen Neuendorffer
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2007)
Keyphrases
  • resource sharing
  • verilog hdl
  • real time
  • resource allocation
  • grid computing
  • computer systems
  • load balancing
  • user experience
  • communication channels
  • grid systems