A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology.

Martin Saint-Laurent Animesh Datta

Published in: ISLPED (2010)

Keyphrases

low power
low voltage
nm technology
cmos technology
power dissipation
power consumption
power management
power reduction
low cost
high speed
mixed signal
energy efficiency
digital signal processing
energy saving
random access memory
power saving
image sensor
design considerations
energy efficient