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A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy.

Kyomin SohnYoung-Ho SuhYoung-Jae SonDaesik YimKang-Young KimDae-Gi BaeTed KangHoon LimSoon-Moon JungHyun-Geun ByunYoung-Hyun JunKinam Kim
Published in: ISSCC (2008)
Keyphrases
  • cmos technology
  • input output
  • high speed
  • garbage collection
  • low power
  • power consumption
  • times faster
  • nm technology
  • multiple description coding
  • data structure
  • low cost
  • high frequency
  • inter mode decision