An Efficient Timing Model for CMOS Combinational Logic Gates.
Chung-Yu WuJen-Sheng HwangChin ChangChing-Chu ChangPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1985)
Keyphrases
- computational model
- formal model
- image sequences
- sensitivity analysis
- low cost
- parameter estimation
- high speed
- management system
- data model
- high level
- probabilistic model
- learning algorithm
- prior knowledge
- video sequences
- objective function
- theoretical framework
- mathematical model
- statistical model
- power consumption
- image segmentation