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Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems.
Tobias Dörr
Timo Sandmann
Florian Schade
Falco K. Bapp
Jürgen Becker
Published in:
ARC (2019)
Keyphrases
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parallel architectures
high speed
field programmable gate array
learning algorithm
computer systems
parallel processing
single processor
real time
data sets
database systems
fpga device