Area-Delay-Efficeint FPGA Design of 32-bit Euclid's GCD based on Sum of Absolute Difference.

Saeideh Nabipour Masoume Gholizade Nima Nabipour

Published in: CoRR (2021)

Keyphrases

absolute difference
design process
verilog hdl
image processing
low cost
spatio temporal
feature vectors
high speed
signal processing
single chip
distortion measure
fpga implementation
fpga device
hardware architectures