A reconfigurable macro-pipelined DCT/IDCT accelerator.
Wenqi BaoJiang JiangQing SunYuzhuo FuPublished in: ASICON (2011)
Keyphrases
- discrete cosine transform
- field programmable gate array
- image compression
- dct coefficients
- low cost
- low power consumption
- transform domain
- compute intensive
- filter bank
- dct domain
- hardware implementation
- embedded systems
- general purpose
- parallel implementation
- parallel computing
- image blocks
- video coding standard
- real time
- efficient implementation
- massively parallel
- multiscale